DRAM Layout Engineer: Lead IP Layout & Verification

Micron Technology, Inc in Tlaquepaque, Jalisco is seeking a DRAM Design Tech Layout Engineer to contribute to the design and development of IP layouts for DRAM chips. The role demands collaboration with global engineering teams and strong leadership in layout execution.

The ideal candidate will hold a BE/BTech or MTech in Electronic/VLSI Engineering and have over 3 years of experience in layout design, ensuring projects meet strict quality and performance standards.

The position includes a comprehensive benefits package, emphasizing equity and support for employees’ work-life balance.